1. Field of the Invention
The present invention relates to a network in CML technology for processing data having a large data bit-width, and in particular to such a network which comprises a transmitter having a predetermined loadability and a plurality of receivers having differential amplifiers (current switches) in two or three series-gating stages, whereby the total number of receivers considerably exceeds the loadability of the transmitter and the total number of the receivers is divided into groups of n2 receivers each.
2. Description of the Prior Art
In large data processing systems, the data to be processed have considerable bit-widths (lengths) of, for example, 72 bits which must be processed in parallel. With an increase in degree of integration and a growing number of terminal pins, it becomes possible to process large portions of, or even the full data word in parallel, in a large scale integrated circuit (LSI). The result of this internally, is that in resigers and multiplexers, for example, the control signal must select n inputs of logic elements (clock or address inputs, for example) for a data word having the bit-width n.
The number of inputs of connected receivers controllable by a transmitter, the so-called fan out, is limited by the loadability of the transmitter and is likewise rigidly prescribed given in integrated circuits which are manufactured in accordance with the master-slice method and contain a supply of components divided into a plurality of areas having prescribed dimensioning. The fan-out n1 of the sub-circuits or cells usually selectable with the assistance of a cell library, of the sub-circuits comprising bipolar transistors in CML technology, predominantly amounts to about eight. This value also forms the basis for the following comments, whereby the same considerations hold true, of course, for deviating values.
Given large bit-widths n, the number of receivers is frequently far greater than the allowable fan-out n1 of the transmitter. It is then possible to employ additional amplifiers which are controlled by the transmitter and which, in turn, respectively control n1 receivers. In this manner, therefore, (n1).sup.2 receivers can be supplied. OR gates in FIG. 1 are usually employed as amplifiers. Such a network comprises the structures schematically illustrated in FIG. 2 having a transmitter S, amplifiers V and receivers E.
What is disadvantageous in the utilization of amplifiers is the increase of the signal delay time, the power dissipation and the number of cells. Added thereto is that amplifiers must be connected in series given more than (n1).sup.2 receivers.
A further possibility for increasing the number of receivers controllable by transmitter is comprised in enlarging the fan-out of the circuit cell serving as a transmitter. The selection thereby remains limited to twice or three times the driver capability, since the number of components required in such circuit cells increases greatly. Although the signal delay time is not initially enlarged, additional amplifiers must again be provided in those cases in which even the increased driver capability is not adequate to drive all existing receivers.
The structure of a network comprising a transmitter SV having k times the driver capability is schematically illustrated in FIG. 3.